
Ph.D. Researcher in Computer Engineering with a focus on hardware security, particularly Trojan detection using delay-based techniques that mitigate the effects of process variations in post-silicon designs. Experienced in both post-silicon and pre-silicon detection approaches, including FPGA-based prototyping and Graph Neural Networks for RTL-level threat modeling. Developed synchronized hardware/software co-designed systems for fault injection testing. In addition to research, served as a lead teaching assistant for multiple undergraduate and graduate-level courses over several years. Currently seeking to contribute to advanced hardware security research as a postdoctoral fellow, with emphasis on resilient detection methodologies and low-cost testing infrastructures.